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AIRCC Digital Library |
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Digital Signal And Image Processing
VLSICS
ISSN : 0976 - 1357 (Online) ; 0976 - 1527 (print)
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| Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby |
| Chien-Cheng Yu and Ming-Chuen Shiau, Hsiuping University of Science and Technology, Taiwan |
| Volume : 7 volume number : 4 pdf |
| Design of Digital PLL Using Optimized Phase Noise VCO |
| Purnima1, Radha B.L1 and Kumaraswamy K.V2, 1Bangalore Institute of Technology, India and 2Trident Techlabs Private limited, India |
| Volume : 7 volume number : 4 pdf |
| Implementation of SDC-SDF Architecture for Radix-4 FFT |
| G. Deeshma Venkatakanakadurga and G. R. L. V. N. Srinivasaraju, Shri Vishnu Engineering College for Women, India |
| Volume : 7 volume number : 4 pdf |
| Leakage Reduction Technique and Analysis of CMOS D Flip Flop |
| Sridhara K and G S Biradar, P D A College of Engineering, India |
| Volume : 7 volume number : 4 pdf |
| Glitch Analysis and Reduction in Digital Circuits |
| Ronak Shah, Dharmsinh Desai University, India |
| Volume : 7 volume number : 4 pdf |
| Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Technique |
| Simran Khokha1 and K.Rahul Reddy2, 1University of Delhi, India and 2Sharda University, India |
| Volume : 7 volume number : 4 pdf |